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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.4. INDEX: USB0 Endpoint Index
Bit
7
6
5
4
3
2
1
0
Name
EPSEL[3:0]
Type
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x0E
Bit Name
Function
7:4
3:0
Unused
EPSEL[3:0]
Read = 0000b. Write = don’t care.
Endpoint Select Bits.
These bits select which endpoint is targeted when indexed USB0 registers are
accessed.
0000: Endpoint 0
0001: Endpoint 1
0010: Endpoint 2
0011: Endpoint 3
0100-1111: Reserved.
21.4. USB Clock Configuration
USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is
selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock
must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options
are described in Section “19. Oscillators and Clock Selection” on page 142. The USB0 clock is selected via
SFR CLKSEL (see SFR Definition 19.1).
Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows
the internal oscillator to meet the requirements for USB clock tolerance. Clock Recovery should be used in
the following configurations:
Communication Speed
Full Speed
Low Speed
USB Clock
Internal Oscillator
Internal Oscillator / 8
When operating USB0 as a Low Speed function with Clock Recovery, software must write 1 to the CRLOW
bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode.
Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres-
ent on the USB network. This mode is not required (or recommended) in typical USB environments.
Rev. 1.4
179
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